In the field of ultrathin integrated circuit or semiconductor wafers, the separation of such ultrathin integrated circuit wafers may result in back side and front side chipping. In particular, a mechanical robustness and flexibility of a die may be reduced due to the low thickness of the wafers. Back end of line layers of advanced semiconductor device wafers, e.g. of advanced CMOS devices, are covered with metals, e.g. copper, dielectric materials, e.g. low k materials, and other materials like silicon nitride as a passivation material and/or aluminum for chip finishing, and/or bond pads. The design rules for advanced semiconductor device wafers require a dense coverage of metal (e.g. copper, aluminum, etc) tiles in order to fulfill homogeneity and planarization demands. The ubiquitous metal coverage dominates the mechanical behavior of the semiconductor wafer and/or chip when a thickness of a substrate, e.g. silicon, reduced to a thickness smaller than 150 micrometers. The semiconductor wafer and/or chip behave like composite of a flexible silicon spring with a ductile metal multi layer on top of it. For ultrathin semiconductor wafers, in particular, when a thickness of the metal/dielectrical layers approaches a thickness of a remaining silicon substrate, a mechanical blade dicing process may not reach a high process capability. The reason may be a strong clogging or strong coverage of the dicing blade with metal, e.g. copper.
Alternative laser separation or even dry (trench) etching processes that could overcome the issue of mechanical chip weakness may not be applied on the wafer front side, because the metal structures may shield laser separation or even dry (trench) etching processes.